Volume 5, Number 15, Pages 1 – 32 (In Progress), January - March, 2017

Table of Contents

Previous

About the Cover

The performance requirement of modern devices and systems are growing exponentially. Therefore, the number of components and Hardware requirements are also going high. Unfortunately, the existing methodology and technological advancement is not adequate to provide enough support. Therefore, the need for a much faster and efficient design method should be employed. Hence we introduce the concept of Network on Chip (NOC). By which we can overcome the disadvantage of existing Bus architecture. In bus architecture as we already know data transfer between different parts of the system occur via buses. This mode of communication is not much efficient and has slow bus response and also scalability problem. On the other hand, Network on Chip architecture increases the efficiency of communication between different modules. Its significantly reduces the amount of wire required to route data between modules and has high operating frequency and increased scalability. The objective of this paper is to introduce some concepts of Network on Chip (NOC) architecture involving the comparison of different routing strategies in Network on Chip (Ref: Savieo sebastian, Harikrishna Sabu, Midhunlal Sobhanan, Nigil M Kurian, Sanju V. Comparison of Different Routing Strategies in Network on Chip (NOC). Discovery Engineering, 2017, 5(15), 9-16), (Image: wyss.harvard.edu).

ANALYSIS

An Approach to Clustering of Text Documents with n-Texts Input Using Graph Mining Techniques

Bapuji Rao, Sabari Giri Murugan

The authors propose a simple approach of clustering of text documents with a given n-words input using graph mining techniques. This proposed approach clusters text documents in three forms based on identifying of n-words, (n-1)-words, and (n-2)-words respectively from text documents. These three forms of clustering of text documents with identifying all the n-words, (n-1)-words, and (n-2)-words from n-words input forms from set of text documents. These three forms of clustering are treated as documentword relation and finally represented as bi-partite graphs. For this the authors have proposed an algorithm for three forms of clustering of text documents for a given n-words input using graph mining techniques. Finally, the paper concludes with the result analysis of the proposed algorithm by implementing the proposed technique using C++ programming language and observed satisfactory results.

Discovery Engineering, 2017, 5(15), 1-8

Full Text | PDF

ANALYSIS

Comparison of Different Routing Strategies in Network on Chip (NOC)

Savieo sebastian, Harikrishna Sabu, Midhunlal Sobhanan, Nigil M Kurian, Sanju V

The performance requirement of modern devices and systems are growing exponentially. Therefore, the number of components and Hardware requirements are also going high. Unfortunately, the existing methodology and technological advancement is not adequate to provide enough support. Therefore, the need for a much faster and efficient design method should be employed. Hence we introduce the concept of Network on Chip (NOC). By which we can overcome the disadvantage of existing Bus architecture. In bus architecture as we already know data transfer between different parts of the system occur via buses. This mode of communication is not much efficient and has slow bus response and also scalability problem. On the other hand, Network on Chip architecture increases the efficiency of communication between different modules. Its significantly reduces the amount of wire required to route data between modules and has high operating frequency and increased scalability. The objective of this paper is to introduce some concepts of Network on Chip (NOC) architecture involving the comparison of different routing strategies in Network on Chip.

Discovery Engineering, 2017, 5(15), 9-16

Full Text | PDF

ANALYSIS

A Guide for Building Simulators for Butterfly and Fattree Architectures

Arjun RC, Megha Mohan, Anchu Jossy, Akshai George, Sanju V

To meet the growing computation-intensive applications and the needs of low-power, high-performance systems, the number of computing resources in single-chip has enormously increased, because current VLSI technology can support such an extensive integration of transistors. By adding many computing resources such as CPU, DSP, specific IPs, etc. to build a system in System-on- Chip, its interconnection between each other becomes another challenging issue. As an improvement on SoC, a new paradigm has been introduced called NoC. NoC is an intercommunication based network system, which is implemented on an integrated circuit, typically between IP cores in a SoC. With the development of IC technology, SoC fails to meet the increasing requirement of network communication since it is based on traditional bus architecture. With the transplantation of network technology from computer systems and the replacement of traditional bus structure with network structure, which solves the communication bottleneck issue of SoC and is rather promising. This paper is about the design and development of a simulator for NoC architectures. More specifically butterfly and fattree architectures.

Discovery Engineering, 2017, 5(15), 17-21

Full Text | PDF

COMMUNICATION

Power Efficient Dishwasher

Kaushik J Prakash, Aditya Umesh Prabhugaunkar

Dishwasher is a machine that facilitates the washing of utensils and cutlery during its operation. We had observed that household and traditional way of washing utensils was a very cumbersome process that led to waste of time and energy. We conducted a market research on various dishwashers present in India and observed that dishwasher present have low power efficiency. This paper explores the design decisions and steps implemented in achieving a customized power efficient dishwasher.

Discovery Engineering, 2017, 5(15), 22-26

Full Text | PDF

ANALYSIS

Design of internal expanding brake system for controlling high end rpm of turbines

Sree Krishna Guthena

In this concept the internal expanding brake system works on the principle of centrifugal force (under no load condition). This internal expanding brake system is similar to that of mechanical brake system, which is used to control the speed of the turbine when it is rotating at its maximum speed ranges from 5000 to 6000 rpm. The main advantage of this new brake system is to reduce the vibrations by proper balancing of the mass on both sides by use of brake shoes and there will be no sudden impact because as this brake type used is disc & drum type system. This brake system can be applied to any high speed rotating devices or machines. This paper unfolds the steps involved in the design of brake system for controlling high end speeds based on centrifugal action.

Discovery Engineering, 2017, 5(15), 27-32

Full Text | PDF